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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADV7197 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 multiformat hdtv encoder with three 11-bit dacs functional block diagram test pattern generator and delay y0?9 cr0?r9 cb0?b9 sync generator timing generator i 2 c mpu port clkin horizontal sync vertical sync blanking reset ADV7197 dac control block dac a (y) dac b dac c v ref r set comp 11-bit + sync dac 11-bit dac 11-bit dac chroma 4:2:2 to 4:4:4 (ssaf) chroma 4:2:2 to 4:4:4 (ssaf) features input formats ycrcb in 2 10-bit (4:2:2) or 3 10-bit (4:4:4) format compliant to smpte274m (1080i), smpte296m (720p) and any other high-definition standard using async timing mode rgb in 3 10-bit 4:4:4 format output formats yprpb hdtv (eia-770.3) rgb levels compliant to rs-170 and rs-343a 11-bit + sync (dac a) 11-bit dacs (dac b, c) programmable features internal test pattern generator with color control y/c delay ( ) individual dac on/off control vbi open control i 2 c filter 2-wire serial mpu interface single supply 5 v/3.3 v operation 52-lead mqfp package applications hdtv display devices hdtv projection systems digital video systems high resolution color graphics image processing/instrumentation digital radio modulation/video signal reconstruction * adv is a registered trademark of analog devices, inc. general description the ADV7197 is a triple, high-speed, digital-to-analog encoder on a single monolithic chip. it consists of three high-speed video d/a converters with ttl-compatible inputs. the ADV7197 has three separate 10-bit-wide input ports that accept data in 4:4:4 10-bit ycrcb or rgb, or 4:2:2 10-bit ycrcb. t his data is accepted in hdtv format at 74.25 mhz or 74.1758 mhz. for any other high definition standard but smpte274m or smpte296m, the async timing mode can be used to input data to the ADV7197. for all standards, external horizontal, vertical, and blanking signals or eav/sav codes control the insertion of appropriate synchronization sig nals into the digital data stream and therefore the output signals. the ADV7197 outputs analog yprpb hdtv complying to eia-770.3, or rgb complying to rs-170/rs-343a. the ADV7197 requires a single 5 v/3.3 v power supply, an optional external 1.235 v reference, and a 74.25 mhz (or 74.1758 mhz) clock. the ADV7197 is packaged in a 52-lead mqfp package.
rev. 0 C2C ADV7197?pecifications 5 v specifications 1 parameter min typ max unit test conditions static performance resolution 11 bits integral nonlinearity 1.5 lsb differential nonlinearity 0.9 2.0 lsb guaranteed monotonic digital outputs output high voltage, v oh 2.4 v i source = 400 a output low voltage, v ol 0.4 v i sink = 3.2 ma three-state leakage current 10 av in = 0.4 v three-state output capacitance 4 pf digital and control inputs input high voltage, v ih 2.0 v input low voltage, v il 0.8 v input leakage current 0 1 av in = 0.4 v or 2.4 v input capacitance, c in 4pf analog outputs full-scale output current 3.92 4.25 4.56 ma dac a 2.54 2.83 3.11 ma dac b, c output current range 3.92 4.25 4.56 ma dac a 2.39 2.66 2.93 ma dac b, c dac-to-dac matching 1.4 % dac a, b, c output compliance range, v oc 1.4 v output impedance, r out 100 k ? output capacitance, c out 7pf voltage reference (external and internal) reference range, v ref 1.112 1.235 1.359 v power requirements i dd 2 96 102 ma with f clk = 74.25 mhz i aa 3, 4 11 15 ma power supply rejection ratio 0.01 %/% notes 1 guaranteed by characterization. 2 i dd or the circuit current is the continuous current required to drive the digital core. 3 i aa is the total current required to supply all dacs including v ref circuitry. 4 all dacs on. specifications subject to change without notice. (v aa = 4.75 v to 5.25 v, v ref = 1.235 v, r set = 2470 , r load = 300 . all specifications t min to t max [0 c to 70 c] unless otherwise noted.)
rev. 0 C3C ADV7197 3.3 v specifications 1 parameter min typ max unit test conditions static performance resolution 11 bits integral nonlinearity 1.5 lsb differential nonlinearity 0.9 2.0 lsb digital outputs output high voltage, v oh 2.4 v i source = 400 a output low voltage, v ol 0.4 v i sink = 3.2 ma three-state leakage current 10 av in = 0.4 v three-state output capacitance 4 pf digital and control inputs input high voltage, v ih 2v input low voltage, v il 0.8 0.65 v input leakage current 0 1 av in = 0.4 v or = 2.4 v input capacitance, c in 4pf analog outputs full-scale output current 3.92 4.25 4.56 ma dac a 2.54 2.83 3.11 ma dac b, c output current range 3.92 4.25 4.56 ma dac a 2.39 2.66 2.93 ma dac b, c dac-to-dac matching 1.4 % dac a, b, c output compliance range, v oc 0 1.4 v output impedance, r out 100 k ? output capacitance, c out 7pf voltage reference (external) reference range, v ref 1.112 1.235 1.359 v power requirements i dd 2 46 ma with f clk = 74.25 mhz i aa 3, 4 11 15 ma power supply rejection ratio 0.01 %/% notes 1 guaranteed by characterization. 2 i dd or the circuit current is the continuous current required to drive the digital core. 3 i aa is the total current required to supply all dacs including v ref circuitry. 4 all dacs on. specifications subject to change without notice. (v aa = 3.15 v to 3.45 v, v ref = 1.235 v, r set = 2470 , r load = 300 . all specifications t min to t max [0 c to 70 c] unless otherwise noted.)
rev. 0 C4C ADV7197?pecifications 5 v dynamic?pecifications parameter min typ max unit luma bandwidth 13.5 mhz chroma bandwidth 6.75 mhz signal-to-noise ratio 64 db luma ramp unweighted chroma/luma delay inequality 0 ns specifications subject to change without notice. 3.3 v dynamic?pecifications parameter min typ max unit luma bandwidth 13.5 mhz chroma bandwidth 6.75 mhz signal-to-noise ratio 64 db luma ramp unweighted chroma/luma delay inequality 0 ns specifications subject to change without notice. 5 v timing?pecifications p arameter min typ max unit conditions mpu port 1 sclock frequency 10 400 khz sclock high pulsewidth, t 1 0.6 s sclock low pulsewidth, t 2 1.3 s hold time (start condition), t 3 0.6 s after this period the 1st clock is generated setup time (start condition), t 4 0.6 s relevant for repeated start condition data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 s reset low time 100 ns analog outputs analog output delay 2 10 ns analog output skew 0.5 ns clock control and pixel port 3 f clk 74.25 mhz hdtv mode t clk 81 mhz async timing mode clock high time, t 9 5 1.5 ns clock low time, t 10 5 2.0 ns data setup time, t 11 2.0 ns data hold time, t 12 4.5 ns control setup time, t 11 7ns control hold time, t 12 4.0 ns pipeline delay 16 clock cycles for 4:4:4 pixel input format notes 1 guaranteed by characterization. 2 output delay measured from the 50% point of the rising edge of clock to the 50% point of dac output full-scale transition. 3 data: cb/cr (9:0), cr (9:0), y (9:0); control: hsync / sync , vsync /tsync; dv specifications subject to change without notice. (v aa = 4.75 v to 5.25 v, v ref = 1.235 v, r set = 2470 , r load = 300 . all specifications t min to t max [0 c to 70 c] unless otherwise noted.) (v aa = 3.15 v to 3.45 v, v ref = 1.235 v, r set = 2470 , r load = 300 . all specifications t min to t max [0 c to 70 c] unless otherwise noted.) (v aa = 4.75 v to 5.25 v, v ref = 1.235 v, r set = 2470 , r load = 300 . all specifications t min to t max [0 c to 70 c] unless otherwise noted.)
rev. 0 C5C ADV7197 3.3 v timing?pecifications p arameter min typ max unit conditions mpu port 1 sclock frequency 10 400 khz sclock high pulsewidth, t 1 0.6 s sclock low pulsewidth, t 2 1.3 s hold time (start condition), t 3 0.6 s after this period the 1st clock is generated setup time (start condition), t 4 0.6 s relevant for repeated start condition data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 s reset low time 100 ns analog outputs 2 analog output delay 10 ns analog output skew 0.5 ns clock control and pixel port 3 f clk 74.25 mhz hdtv mode t clk 81 mhz async timing mode clock high time, t 9 51.5 ns clock low time, t 10 52.0 ns data setup time, t 11 2.0 ns data hold time, t 12 4.5 ns control setup time, t 11 7ns control hold time, t 12 4.0 ns pipeline delay 16 clock cycles for 4:4:4 pixel input format notes 1 guaranteed by characterization. 2 output delay measured from the 50% point of the rising edge of clock to the 50% point of dac output full-scale transition. 3 data: cb/cr (9:0), cr (9:0), y (9:0); control: hsync / sync , vsync /tsync; dv specifications subject to change without notice. (v aa = 3.15 v to 3.45 v, v ref = 1.235 v, r set = 2470 , r load = 300 . all specifications t min to t max [0 c to 70 c] unless otherwise noted.) clock pixel input data y0 cb0 y1 cr0 y2 cb1 cr1 ... ... ... yxxx cbxxx yxxx crxxx t 11 t 12 t 9 t 10 t 9 clock high time t 10 clock low time t 11 data setup time t 12 data hold time figure 1. 4:2:2 input data format timing diagram
rev. 0 ADV7197 C6C cr0 cr1 cr2 cr3 ... crxxx clock pixel input data y0 cb0 y1 cb1 y2 cb2 cb3 ... ... ... yxxx cbxxx yxxx cbxxx t 11 t 12 t 9 t 10 crxxx t 9 clock high time t 10 clock low time t 11 data setup time t 12 data hold time figure 2. 4:4:4 ycrcb input data format timing diagram b0 b1 b2 b3 ... bxxx bxxx clock pixel input data r0 g0 r1 g1 r2 g2 g3 ... ... ... rxxx gxxx rxxx gxxx t 11 t 12 t 9 t 10 t 9 clock high time t 10 clock low time t 11 data setup time t 12 data hold time figure 3. 4:4:4 rgb input data format timing diagram
rev. 0 ADV7197 C7C vsync hsync dv yyyy pixel data cr cr cr cr cb cb cb cb a b a min = 44 clk cycles for 1080i a min = 70 clk cycles for 720p b min = 236 clk cycles for 1080i b min = 300 clk cycles for 720p figure 4. input timing diagram t 3 t 2 t 6 t 1 t 7 t 3 t 4 t 8 sda scl t 5 figure 5. mpu port timing diagram
rev. 0 ADV7197 C8C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADV7197 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v voltage on any digital pin . . . . gnd ?0.5 v to v aa + 0.5 v ambient operating temperature (t a ) . . . . . 40 c to +85 c storage temperature (t s ) . . . . . . . . . . . . . . 65 c to +150 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . 150 c infrared reflow soldering (20 secs) . . . . . . . . . . . . . . . 225 c vapor phase soldering (1 minute) . . . . . . . . . . . . . . . . 220 c i out to gnd 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to v aa pin configuration 52 51 50 49 48 43 42 41 40 47 46 45 44 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 13 12 pin 1 identifier top view (not to scale) 39 38 37 36 35 34 33 32 31 30 29 28 27 ADV7197 cr[0] cr[1] cr[2] cr[3] cr[4] cr[5] cr[6] cr[7] cr[8] cr[9] v aa clkin agnd gnd cb/cr[0] cb/cr[1] cb/cr[2] cb/cr[3] cb/cr[4] cb/cr[5] cb/cr[6] cb/cr[7] cb/cr[8] cb/cr[9] alsb reset v dd y[0] y[1] y[2] y[3] y[4] y[5] y[6] y[7] y[8] y[9] v dd gnd v ref r set comp dac b v aa dac a agnd dac c sda scl hsync / sync vsync /tsync dv ordering guide model temperature range package description package option ADV7197kst 0 c to 70 c plastic quad flatpack (mqfp) s-52 notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 analog output short circuit to any power supply or common can be of an indefinite duration.
rev. 0 ADV7197 C9C pin function descriptions pin mnemonic input/output function 1, 12 v dd p digital power supply. 2?1 y0?9 i 10-bit hdtv input port for y data. g data input in rgb mode. 13, 52 gnd g digital ground 14?3 cr0?r9 i 10-bit hdtv input port for color data in 4:4:4 input mode. in 4:2:2 mode this input port is not used. r data input in rgb mode. 24, 35 v aa p analog power supply. 25 clkin i pixel clock input. requires a 74.25 mhz (74.1758 mhz) reference clock. 26, 33 agnd g analog ground 27 dv i video blanking control signal input. 28 vsync/ i vsync , vertical sync control signal input or tsync input control signal in tsync async timing mode. 29 hsync/ sync i hsync , horizontal sync control signal input or sync input control signal in async timing mode. 30 scl i mpu port serial interface clock input. 31 sda i/o mpu port serial data input/output. 32 dac c o color component analog output of input data on cb/cr9? input pins. 34 dac a o y analog output. 36 dac b o color component analog output of input data on cr9?r0 input pins. 37 comp o compensation pin for dacs. connect 0.1 f capacitor from comp pin to v aa . 38 r set i a 2470 ? resistor (for input ranges 64?40 and 64?60, output standards eia-770.3) must be connected from this pin to ground and is used to control the amplitudes of the dac outputs. for input ranges 0?023 (output st andards rs-170, rs-343a) the r set value must be 2820 ? . 39 v ref i/o optional external voltage reference input for dacs or voltage reference output (1.235 v). 40 reset i this input resets the on-chip tim ing generator and sets the ADV7197 into default register setting. reset is an active low signal. 41 alsb i ttl address input. this signal sets up the lsb of the mpu address. when this pin is tied high, the i 2 c filter is activated which reduces noise on the i 2 c interface. when this pin is tied low, the input bandwidth on the i 2 c interface is increased. 42?1 cb/cr9? i 10-bit hdtv input port for color data. in 4:2:2 mode the multiplexed crcb data must be input on these pins. b data input in rgb mode.
rev. 0 ADV7197 C10C functional description digital inputs the digital inputs of the ADV7197 are ttl-compatible. 30-bit ycrcb or rgb pixel data in 4:4:4 format or 20-bit ycrcb pixel data in 4:2:2 format is latched into the device on the rising edge of each clock cycle at 74.25 mhz or 74.1758 in hdtv mode. it is recommended to input data in 4:2:2 mode to make use of the chroma ssafs on the ADV7197. as can be seen in the figures below, these filters have 0 db passband response and prevent signal components being folded back into the frequency band. in 4:4:4 input mode, the video data is already interpo- lated by an external input device and the chroma ssafs of the ADV7197 are bypassed. rbw 10khz vbw 300hz swp 17.0sec start 100khz stop 20.00mhz rl 10.0dbm 10db/ 3.18mhz atten 10db vavg 1 mkr 0db figure 6. ssaf response to a 2.5 mhz chroma sweep using 4:2:2 input mode rbw 10khz vbw 300hz swp 17.0sec start 100khz stop 20.00mhz rl 10.0dbm 10db/ 3.12mhz atten 10db vavg 4 mkr 3.00db figure 7. conventional filter response to a 2.5 mhz chroma sweep using 4:4:4 input mode control signals the ADV7197 accepts sync control signals accompanied by valid 4:2:2 or 4:4:4 data. these external horizontal, vertical and blanking pulses (or eav/sav codes) control the insertion of appropriate sync information into the output signals. analog outputs the analog y signal is output on the 11-bit + sync dac a, the color component analog signals on the 11-bit dacs b, c conforming to eia-770.3 standards r set has a value of 2470 ? (eia-770.3), r load has a value of 300 ? . for the outputs to con- form to rs-170/rs-343a standards r set must have a value of 2820 ? . internal test pattern generator the ADV7197 can generate a cross-hatch pattern (white lines against a black background). additionally, the ADV7197 can output a uniform color pattern. the color of the lines or uni- form field/frame can be programmed by the user. y/crcb delay the y output and the color component outputs can be delayed wrt the falling edge of the horizontal sync signal by up to four clock cycles. i 2 c filter a selectable internal i 2 c filter allows significant noise reduction on the i 2 c interface. for setting alsb high, the input band- width on the i 2 c lines is reduced and pulses of less than 50 ns are not passed to the i 2 c controller. setting alsb low allows greater input bandwidth on the i 2 c lines. mpu port description the ADV7197 support a 2-wire serial (i 2 c-compatible) micro- processor bus driving multiple periphe rals. two inputs serial data (sda) and serial clock (scl) carry information between any device connected to the bus. each slave device is recognized by a unique address. the ADV7197 has four possible slave addresses for both read and write operations. these are unique addresses for each device and are illustrated in figure 8. the lsb sets either a read or write operation. logic level ??corresponds to a read operation while logic level ??corresponds to a w rite opera tion. a1 is set by setting the alsb pin of the ADV7197 to logic level ? or logic level ?.?when alsb is set to ?, there is greater input bandwidth on the i 2 c lines, which allows high-speed data transfers on this bus. when alsb is set to ?, there is reduced input bandwidth on the i 2 c lines, which means that pulses of less than 50 ns will not pass into the i 2 c internal controller. this mode is recommended for noisy systems. 0 x 1 0 1 01 a1 read/write control 0 write 1read address control set up by alsb figure 8. slave address to control the various devices on the bus the following protocol must be followed. first the master initiates a data transfer by establishing a start condition, defined by a high-to-low transi- tion on sda while scl remains high. this indicates that an address/data stream will follow. all peripherals respond to the start condition and shift the next eight bits (7 -bit address + r/ w bit). the bits are transferred from msb down to lsb. the periph- eral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sda and scl lines w aiting for the start condition and the correct transmitted address. the r/ w bit determines the direction of the data.
rev. 0 ADV7197 C11C a logic ??on the lsb of the first byte means that the master will write information to the peripheral. a logic ??on the lsb of the first byte means that the master will read i nformation from the peripheral. the ADV7197 acts as a standard slave device on the bus. the data on the sda pin is 8 bits long supp orting the 7-bit addresses plus the r/ w bit. it interprets the first byte as the device address and the second byte as the starting subaddress. the subaddresses auto-increment, allowing data to be written to or read from the starting subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subad- dress register on a one-by-one basis without having to update all the registers. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. during a given scl high period the user should issue only one start condition, one stop condition or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the ADV7197 will not issue an acknowledge and will return to the idle condition. if in auto-increment m ode, the user exceeds the hi ghest subaddress, the following action will be taken: 1. in read mode, the highest subaddress register contents will continue to be output until the master device issues a no-acknowledge. this indicates the end of a read. a no- acknowledge condition is where the sda line is not pulled low on the ninth pulse. 2. in write mode, the data for the invalid byte will be not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7197 and the part will return to the idle condition. data a(s) s slave addr a(s) sub addr a(s) lsb = 0 lsb = 1 data a(s) p s slave addr a(s) sub addr a(s) s slave addr a(s) data a(m) a (m ) data p write sequence read sequence s = start bit a(s) = acknowledge by slave a (s) = no-acknowledge by slave p = stop bit a(m) = acknowledge by master a (m) = no-acknowledge by master figure 10. write and read sequence sr4 sr3 sr2 sr1 sr0 sr7 sr6 sr5 address sr6 sr5 sr4 sr3 sr2 sr1 sr0 00h 0000000 mode regi ster 0 01h 0000001 mode regi ster 1 02h 0000010 mode regi ster 2 03h 0000011 mode regi ster 3 04h 0000100 mode regi ster 4 05h 0000101 mode regi ster 5 06h 0000110 color y 07h 0000111 color cr 08h 0001000 color cb ADV7197 subaddress register zero should be written here sr7 figure 11. subaddress registers 1 7 8 9 89 8 9 p s start addr r/ w ack subaddress ack data ack stop sdata sclock 1 71 7 figure 9. bus data transfer figure 9 illustrates an example of data transfer for a read sequence and the start and stop conditions. figure 10 shows bus write and read sequences. register accesses the mpu can write to or read from all of the registers of the ADV7197 except the sub address registers, which are write-only registers. the subaddress register determines which register is accessed by the next read or write operation. all communications with the part through the bus begin with an access to the subaddress register. a read/write operation is performed from/to the target address which then increments to the next address until a stop command on the bus is performed. register programming the following section describes the functionality of each regis- ter. all registers can be read from as well as written to unless otherwise stated. subaddress register (sr7?r0) the communications register is an eight bit write-only register. after the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place. figure 11 shows the various operations under the control of the subaddress register. ??should always be written to sr7. register select (sr6?r0) these bits are set up to point to the required starting address.
rev. 0 ADV7197 C12C mode register 0 mr0 (mr07?r00) (address (sr4?r0) = 00h) figure 14 shows the various operations under the control of mode register 0. mr0 bit description output standard selection (mr00?r01) these bits are used to select the output levels from the ADV7197. if eia 770.3 (mr01?0 = ?0? is selected, the output levels will be: 0 mv for blanking level, 700 mv for peak white (y channel), 350 mv for pr, pb outputs and ?00 mv for tri-level sync. if full input range (mr01?0 = ?0? is select ed, the output levels will be 700 mv for peak white for the y channel, 350 mv for pr, pb outputs, and ?00 mv for sync. this mode is used for rs-170, rs-343a standard output compatibility. sync insertion on the pr, pb channels is optional. for output levels refer to the appendix. input control signals (mr02?r03) these control bits are used to select whether data is input with external horizontal, vertical, and blanking sync signals or if the data is input with embedded eav/sav codes. an asynchro- nous timing mode is also available using tsync, sync and dv as input control signals. these timing control signals have to be programmed by the user and are used for any other high definition standard input but smpte274m and smpte296m. figure 12 shows an example of how to program the ADV7197 to accept a different high definition standard but smpte274m or smpte296m. reserved (mr04) a ??must be written to this bit. input standard (mr05) select between 1080i or 720p input. dv polarity (mr06) this control bit allows to select the polarity of the dv input control signal to be either active high or active low. this is in order to facilitate interfacing from input devices which use an active high blanking signal output. reserved (mr07) a ??must be written to this bit. clk sync tsync dv set mr06 = 1 programmable input timing analog output active video horizontal sync 81 66 66 243 1920 ab c de figure 12. async timing modeprogramming input control signals for smpte295m compatibility 747 748 749 750 1 2 3 4 5 6 7 8 25 26 27 744 745 display vertical blanking interval display dv vsync h sync figure 13. dv input control signal in relation to video output signal for smpte296m (720p)
rev. 0 ADV7197 C13C table i must be followed when programming the control signals in async timing mode. table i. truth table sync tsync dv 1 ? 0 0 0 or 1 50% point of falling edge of tri-level horizontal sync signal, a 0 0 ? 1 0 or 1 25% point of rising edge of tri-level horizontal sync signal, b 0 ? 1 0 or 1 0 50% point of falling edge of tri-level horizontal sync signal, c 1 0 or 1 0 ? 1 50% start of active video, d 1 0 or 1 1 ? 0 50% end of active video, e mode register 1 mr1 (mr17?r10) (address (sr4?r0) = 01h) figure 15 shows the various operations under the control of mode register 1. mr1 bit description pixel data enable (mr10) when this bit is set to ?,?the pixel data input to the ADV7197 is blanked such that a black screen is output from the dacs. when this bit is set to ?,?pixel data is a ccepted at the input pins and the ADV7197 outputs to the standard set in ?utput standard selection?(mr01?r00). this bit also must be set to 1 to enable output of the test pattern signals. input format (mr11) it is possible to input data in 4:2:2 format or in 4:4:4 format. test pattern enable (mr12) enables or disables the internal test pattern generator. test pattern hatch/frame (mr13) if this bit is set to ?,?a cross hatch test pattern is output from the ADV7197. the cross hatch test pattern can be used to test monitor convergence. if this bit is set to ?,?a uniform colored frame/field test pattern is output from the ADV7197. the color of the lines or the frame/field is by default white but can be programmed to be any color using the color y, color cr, color cb registers. vbi open (mr14) this bit enables or disables the facility of vbi data insertion during the vertical blanking interval. for this purpose lines 7?0 in 1080i and lines 6?5 in 720p can be used for vbi data insertion. reserved (mr15?r17) a ??must be written to these bits. mr11 mr17 mr12 mr14 mr15 mr16 mr13 mr10 mr14 0 disabled 1 enabled vbi open mr12 0 disabled 1 enabled test pattern enable mr10 0 disabled 1 enabled pixel data enable mr13 0hatch 1 field/frame test pattern hatch/frame mr11 0 4:4:4 ycrcb 1 4:2:2 ycrcb input format zero must be written to these bits mr17 mr15 figure 15. mode register 1 mr01 mr07 mr04 mr05 mr06 mr03 mr00 zero must be written to this bit mr04 mr06 0 active high 1 active low dv polarity mr05 0 1080i 1 720p input standard mr03 mr02 00 hsync \ vsync /dv 0 1 eav/sav 1 0 tsync/ sync /dv 1 1 reserved input control signals mr01 mr00 0 0 eia-770.3 0 1 reserved 1 0 full i/p range 1 1 reserved output standard selection zero must be written to this bit mr07 mr02 figure 14. mode register 0
rev. 0 ADV7197 C14C mode register 2 mr1 (mr27?r20) (address (sr4?r0) = 02h) figure 17 shows the various operations under the control of mode register 2. mr2 bit description y delay (mr20?r22) with these bits it is possible to delay the y signal with respect to the falling edge of the horizontal sync signal by up to four pixel clock cycles. figure 16 demonstrates this facility. color delay (mr23?r25) with theses bits it is possible to delay the color signals with respect to the falling edge of the horizontal sync signal by up to four pixel clock cycles. figure 16 demonstrates this facility. reserved (mr26?r27) a ??must be written to these bits. max delay no delay no delay max delay prpb delay y delay y output prpb outputs figure 16. y and color delay mr21 mr27 mr22 mr24 mr25 mr23 mr20 mr26 mr25 mr24 mr23 0 0 0 0 pclk 0 0 1 1 pclk 0 1 0 2 pclk 0 1 1 3 pclk 1 0 0 4 pclk color delay mr22 mr21 mr20 0 0 0 0 pclk 0 0 1 1 pclk 0 1 0 2 pclk 0 1 1 3 pclk 1 0 0 4 pclk y delay zero must be written to these bits mr27 mr26 figure 17. mode register 2 mr37 mr32 mr34 mr36 zero must be written to these bits mr37 mr36 mr34 0 power-down 1 normal dac b control mr35 mr35 0 power-down 1 normal dac c control mr33 mr31 mr30 mr33 0 power-down 1 normal dac a control zero must be written to these bits mr32 mr30 figure 18. mode register 3 mode register 3 mr3 (mr37?r30) (address (sr4?r0) = 03h) figure 18 shows the various operations under the control of mode register 3. mr3 bit description reserved (mr31?r32) a ??must be written to these bits. dac a control (mr33) setting this bit to ??enables dac a, otherwise this dac is powered down. dac b control (mr34) setting this bit to ??enables dac b, otherwise this dac is powered down. dac c control (mr35) setting this bit to ??enables dac c, otherwise this dac is powered down. reserved (mr36?r37) a ??must be written to these bits.
rev. 0 ADV7197 C15C mode register 4 mr4 (mr47?r40) (address (sr4?r0) = 04h) figure 19 shows the various operations under the control of mode register 4. mr4 bit description timing reset (mr40) toggling mr40 from low to high and low again resets the inter- nal horizontal and vertical timing counters. mode register 5 mr5 (mr57?r50) (address (sr4-sr0) = 05h) figure 20 shows the various operations under the control of mode register 5. mr5 bit description reserved (mr50) this bit is reserved for the revision code. rgb mode (mr51) when rgb mode is enabled (mr51 = ?? the ADV7197 accepts unsigned binary rgb data at its input port. this control is also available in async timing mode. sync on prpb (mr52) by default the color component output signals pr, pb do not contain any horizontal sync pulses. they can be inserted when mr52 = ?. this control is not available in rgb mode. mr47 mr42 mr44 mr46 zero must be written to these registers mr47 mr41 mr45 mr43 mr41 mr40 mr40 timing reset figure 19. mode register 4 mr57 mr52 mr56 mr55 mr53 mr50 mr54 mr53 0 dac b = pr 1 dac c = pr color output swap mr52 0 disable 1 enable sync on prpb mr51 0 disable 1 enable rgb mode reserved for revision code mr50 mr51 zero must be written to these bits mr57 mr54 figure 20. mode register 5 color output swap (mr53) by default dac b is configured as the pr output and dac c as the pb output. in setting this bit to ??the dac outputs can be swapped around so that dac b outputs pb and dac c outputs pr. the table below demonstrates this in more detail. this control is also available in rgb mode. reserved (mr54?r57) a ??must be written to these bits. table ii. relationship between color input pixel port, mr53 and dac b, dac c outputs in 4:4:4 input mode color data analog output input on pins mr53 signal cr9? 0 dac b cb/cr9? 0 dac c cr9? 1 dac c cb/cr9? 1 dac b in 4:2:2 input mode color data analog output input on pins mr53 signal cr9? 0 or 1 not operational cb/cr9? 0 dac c (pb) cb/cr9? 1 dac c (pr)
rev. 0 ADV7197 C16C color y cy (cy7?y0) (address (sr4?r0) = 06h) cy7 cy6 cy5 cy4 cy3 cy2 cy1 cy0 cy7?y0 color y value figure 21. color y register color cr ccr (ccr7?cr0) (address (sr4?r0) = 07h) ccr7 ccr6 ccr5 ccr4 ccr3 ccr2 ccr1 ccr0 ccr7 ccr0 color cr value figure 22. color cr register color cb ccb (ccb7?cb0) (address (sr4?r0) = 08h) ccb7 ccb6 ccb5 ccb4 ccb3 ccb2 ccb1 ccb0 ccb7 ccb0 color cb value figure 23. color cb register these three 8-bit-wide registers are used to program the output color of the internal test pattern generator, be it the lines of the cross hatch pattern or the uniform field test pattern. the standard used for the values for y and the color difference signals to obtain white, black and the saturated prim ary and com ple- mentary colors conforms to the itu-r bt 601-4 standard. the table iii shows sample color values to be programmed into the color registers. table iii. sample color values sample color y color cr color cb color value value value white 235 (eb) 128 (80) 128 (80) black 16 (10) 128 (80) 128 (80) red 81 (51) 240 (f0) 90 (5a) green 145 (91) 34 (22) 54 (36) blue 41 (29) 110 (6e) 240 (f0) yellow 210 (d2) 146 (92) 16 (10) cyan 170 (aa) 16 (10) 166 (a6) magenta 106 (6a) 222 (de) 202 (ca) dac termination and layout considerations voltage reference the ADV7197 contains an on-board voltage reference. the v ref pin is normally terminated to v aa through a 0.1 f capacitor when the internal v ref is used. alternatively, the ADV7197 can be used with an external v ref (ad589). resistor r set is connected between the r set pin and analog ground and is used to control the full scale output current and theref ore the dac voltage output levels. for full-scale output r set must have a value of 2470 ? . r load has a value of 300 ? . when an input range of 0?023 is selected the value of r set must be 2820 ? . the ADV7197 has three analog outputs, corresponding to y, pr, pb video signals. the dacs must be used with external buffer circuits in order to provide sufficient current to drive an output device. a suitable op amp would be the ad 8057. pc board layout considerations the adv7 197 is optimally designed for lowest noise perfor- mance, both radiated and conducted noise. to complement the excellent noise performance of the ADV7197, it is imperative that great care be given to the pc board layout. the layout should be optimized for lowest noise on the ADV7197 power and ground lines. this can be achieved by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and agnd and v dd and dgnd pins should be kept as short as possible to minimized inductive ringing. it is recommended that a four-layer printed circuit board is used. with power and ground planes separating the layer of the signal carrying traces of the components and solder side layer. placement of components should consider to separate noisy circuits, such as crystal clocks, high-speed logic circuitry and analog circuitry. there should be a separate analog ground plane (agnd) and a separate digital ground plane (gnd). power planes should encompass a digital power plane (v dd ) and a analog power plane (v aa ). the analog power plane should contain the dacs and all associated circuitry, and the v ref circuitry. the digital power plane should contain all logic circuitry. the analog and digital power planes should be individually connected to the common power plane at one single point through a suit- able filtering device, such as a ferrite bead. dac output traces on a pcb should be treated as transmission lines. it is recommended that the dacs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than 3 inches. the dac termi- nation resistors should be placed as close as possible to the dac outputs and should overlay the pcb? ground plane. as well as minimizing reflections, short analog output traces will reduce noise pickup due to neighboring digital circuitry.
rev. 0 ADV7197 C17C supply decoupling noise on the analog power plane can be further reduced by the use of decoupling capacitors. optimum performance is achieved by the use of 0.1 f ceramic capacitors. each of group of v aa or v dd pins should be indi- vidually decoupled to ground. this should be done by placing the capacitors as close as possible to the device with the capaci- tor leads as short as possible, thus minimizing lead inductance. digital signal interconnect the digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry. digital signal lines should not overlay the analog power plane. due to the high clock rates used, long clock lines to the ADV7197 should be avoided to minimize noise pickup. any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane. analog signal interconnect the ADV7197 should be located as close as possible to the output connectors thus minimizing noise pickup and reflections due to impedance mismatch. for optimum performance, the analog outputs should each have a source termination resistance to ground of 75 ? . this termi- nation resistance should be as close as possible to the ADV7197 to minimize reflections. any unused inputs should be tied to ground. 300 5k 5k mpu bus 4.7k v aa power supply decoupling for each power supply group alsb dv reset clkin r set sda scl dac a v dd vsync /tsync ADV7197 unused inputs should be grounded dac b 100 hsync / sync dac c 27mhz, 74.25mhz or 74.1758mhz clock 4.7k 4.7 f 6.3v 300 300 100 2.47k or 2.82k 10nf 0.1 f y output pr(v) output pb(u) output v ref gnd 13, 52 agnd 26, 33 y0 y9 cr0 cr9 cb/cr0 cb/cr9 0.1 f 10nf 0.1 f 24, 35 1, 12 v dd v aa comp v aa v aa v dd v dd v dd figure 24. circuit layout
rev. 0 ADV7197 C18C video output buffer and optional output filter output buffering is necessary in order to drive output devices, s uch as hdtv monitors. analog devices produces a range of suitable op amps for this application. a suitable op amp would be the ad8057. more information on line driver buffering circuits is given in the rel- evant op amp data sheets. an optional analog reconstruction lpf might be required as an antia lias filter if the ADV7197 is connected to a device that requires this filtering. the eval adv7196/ADV7197eb evaluation board uses the ml6426 microlinear ic, which provides buffering and low-pass filtering for hdtv applications. the eval adv7196/ADV7197eb rev. b and rev. c evaluation boards use the ad 8057 as a buffer and a 6th order lpf. the application note, an-tbd, describes in detail these two designs and should be consulted when designing external filter and buffers for analog devices video encoders. ADV7197 dac a dac b dac c lpf ad8057 5v 75 0.1 f 0.1 f 5v 10 f 75 coax 10 f 75 lpf ad8057 5v 0.1 f 0.1 f +5v 10 f 75 coax 10 f 75 ad8057 5v 0.1 f 0.1 f +5v 10 f 75 coax 10 f 75 lpf hdtv monitor 75 75 figure 25. output buffer and optional filter to calculate the output full-scale current and voltage, the fol- lowing equations should be used: v out = i out r load i out = ( v ref k )/ r set where: k = 5.66 (for input ranges 64?40, 64?60, output standards eia770.3) k = 6.46 (for input ranges 0?023, output standards rs170/343a v ref = 1.235 v.
rev. 0 ADV7197 C19C 940 64 active video 700mv 300mv 300mv output voltage input code eia-770.3, standard for y 0mv 960 64 active video 350mv 300mv 300mv output voltage eia-770.3, standard for pr/pb 0mv 512 350mv figure 26. eia 770.3 standard output signals (1080i, 720p) 1023 64 active video 700mv 0mv 300mv output voltage input code y-output levels for full i/p selections 1023 64 active video 700mv 300mv output voltage prpb-output levels for full i/p selections 0mv input code figure 27. output levels for full i/p selection register settings register settings on power-up address register setting 00hex mode register 0 00hex 01hex mode register 1 00hex 02hex mode register 2 00hex 03hex mode register 3 39hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex color y a0hex 07hex color cr 80hex 08hex color cb 80hex register settings internal colorbars (field), hdtv mode address register setting 00hex mode register 0 00hex 01hex mode register 1 0dhex 02hex mode register 2 00hex 03hex mode register 3 39hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex color y xxhex 07hex color cr xxhex 08hex color cb xxhex f f 0 0 input pixels 0 0 f v h * f f 0 0 f v h * 0 0 c b y c r c r y 4 clock sample number eav code digital active line analog waveform smpte274m 4 clock 2112 2116 2156 0 44 188 192 2111 4t sav code 4t 1920t 272t ancillary data (optional) or blanking code digital horizontal blanking 0 h datum fvh * = fvh and parity bits sav/eav: lines 1 562: f = 0 sav/eav: lines 563 1125: f = 1 sav/eav: lines 1 20; 561 583; 1124 1125: v = 1 sav/eav: lines 21 560; 584 1123: v = 0 2199 figure 28. eav/sav input data timing diagramsmpte274m (1080i)
rev. 0 ADV7197 C20C 747 748 749 750 1 2 3 4 5 6 7 8 25 26 27 744 745 display vertical blanking interval figure 29. smpte296m (720p) 1124 1125 1 2 3 4 5 6 7 8 20 21 22 560 display vertical blanking interval field 1 561 562 563 564 565 566 567 568 569 570 583 584 585 1123 display vertical blanking interval field 2 figure 30. smpte274m (1080i) 52-lead plastic quad flatpack (mqfp) (s-52) top view (pins down) 1 13 14 27 26 39 40 52 pin 1 0.014 (0.35) 0.010 (0.25) 0.557 (14.15) 0.537 (13.65) 0.398 (10.11) 0.390 (9.91) 0.557 (14.15) 0.537 (13.65) 0.398 (10.11) 0.390 (9.91) 0.0256 (0.65) bsc 0.082 (2.09) 0.078 (1.97) 0.012 (0.30) 0.006 (0.15) 0.008 (0.20) 0.006 (0.15) seating plane 0.037 (0.95) 0.026 (0.65) 0.094 (2.39) 0.084 (2.13) outline dimensions dimensions shown in inches and (mm). c02155C1.5C4/01(0) printed in u.s.a.

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